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preliminary information www.fairchildsemi.com features asynchronous loading of control parameters rapid (25ns per pixel) rotation, warping, panning, and scaling of images three-dimensional image addressing capability general third-order polynomial transformations in two dimensions on-chip three-dimensional transformation of up to order 1.5 also supported flexible, user-con?urable pixel datapath timing structure static convolutional ?tering of up to 16 x 16 pixel (one- pass), 256 x 256 pixel (two-pass) or 256 x 256 x 256 pixel (three-pass) windows user-selectable source image subpixel resolution of 2 -8 to 2 -16 pin-compatible upgrade to tmc2302 24-bit (optional 36-bit) positioning precision within the source image space, 48-bit internal precision low power cmos process available in a 120-pin plastic pin grid array and 120-lead metric quad flat pack applications high-performance video special-effects generators guidance systems image recognition robotics high-precision image registration description the TMC2302A, a pin-compatible replacement for the tmc2302, is a high-speed self-sequencing address genera- tor which supports image manipulations such as rotation, rescaling, warping, ?tering, and resampling. it remaps the pixel locations of a target (display) space back into those of a source image space. the degree and type of image manipula- tion is determined by the remapping selected. to remap from the target to the source space, this integrated circuit computes a series of polynomials of the target space coordinates, based on user-assigned coef?ients. two TMC2302A chips can generate third-order warps of a two- dimensional image, whereas three can second-order warp a three-dimensional image. simpli?d block diagram 65-2302-01 asynchronous host interface idat 15-0 iadr 6-0 ics iwr control parameter registers control noop synchronous host interface init sync clk target address generator source address generator source memory interface convolutional control target memory interface sync flags oes sadr 23-0 sval oek acc twr kadr 7-0 oet tval tadr 11-0 end done walk counter TMC2302A image manipulation sequencer 40 mhz rev. 0.9.2
TMC2302A product specification 2 preliminary information description (continued) a system based on two TMC2302As can nearest-neighbor resample a two-dimensional 512 x 512 pixel image in 6.5 milliseconds, translating, rotating, or warping it, depending on the user-selected transformation parameters. a complete bilinear interpolation of the sample image can be completed in 26 milliseconds (or 6.5ms with a tmc2246a companion chip), while a nearest-neighbor resampling of a 3d image 128 pixels on a side takes only 53 milliseconds with three TMC2302As. image resampling speed is independent of angle of rotation, degree of warp, or amount of zoom speci- ?d. the TMC2302A can process image data ?lds with up to 24 bits of binary resolution (2 24 pixels) per dimension, with 0 to 16-bit subpixel resolution. along with the original plastic pin grid array (ppga) package, the TMC2302A is offered in a 120-lead metric quad flatpack (mqfp) as well. all tmc2302 electrical, functional, and environmental speci?ations are improved or remain unchanged in the TMC2302A. block diagram asynchronous host interface synchronous host interface noop internal programmable delay 0 to 7 clocks clock int clk sync source address generator kernel walk offset accumulator 24-bits walk counter 8-bits boundary comparator 36-bits source memory interface 3-d boundary comparator 3 x 13 bits target address generator 3 x 13-bits 48-bits (47-24) (23-12) (7-0) sadr 23-0 kadr 7-0 tadr 11-0 oes x(11-0) y(11-0) z(11-0) 65-2302-02 idat 15-0 iadr 6-0 ics iwr control parameter and address buffer control oek acc oet twr tval end done sval convolutional control target memory interface
product specification TMC2302A 3 preliminary information functional description general information the TMC2302A is a versatile, high-performance address generator which can control, under user direction, ?tering or remapping of two or three-dimensional images by resam- pling them from one set of cartesian coordinates (x, y, z) into a new, transformed set (u, v, w). most applications utilize two identical devices for two-dimensional, or three devices for three-dimensional, image processing. the host cpu initializes the system by loading the input image buffer ram with the source image pixel data and the TMC2302As with the image transformation and system con?uration con- trol parameters. these parameters are loaded by a separate, asynchronous input clock. the ims-based system then exe- cutes the entire transformation as programmed, generating a done ?g upon completion of the transform. the user can program the chip to repeat the transform continuously or to halt at the end. the imss continuously compute the target bit plane (u, v) or bit space addresses (u, v, w) in typical line-by-line, raster- scan serial sequence. for each output pixel address, they compute the corresponding remapped source image coordi- nates, each of whose upper 24 bits become the source bit plane addresses (x, y). an additional lower twelve bits are available through the target address port in the optional extended address mode. source image addresses may be generated at up to 40mhz, with the corresponding target image addresses then appearing at up to (40/k)mhz, where ??is the size of the interpolation kernel implemented. in the two-ims system, one TMC2302A computes the horizontal coordinates x and u while the other generates the y and v (vertical) addresses. in a three-dimensional system, one additional ims would provide the z and w (depth or time) coordinates. to support a wide range of image transformations, the ?ow? or x/u device implements a 16-term polynomial of the form: x = a + bu + cu 2 + du 3 + ev + fvu + gvu 2 + hvu 3 + iv 2 + jv 2 u + kv 2 u 2 + lv 2 u 3 + mv 3 + nv 3 u + ov 3 u 2 + pv 3 u 3 where "a" through "p" are the user-de?ed image transfor- mation parameters. the TMC2302A steps sequentially through the pixels within a user-de?ed rectangle in the tar- get image space, computing the ?ld?source image address (x, y, z) corresponding to each ?ew?target image pixel (u, v, w). user-programmable ?gs are available to indicate when the source and target image addresses have fallen out- side of a de?ed rectangular area, simplifying the generation of complex images or image windows. here, u = u-umin and v = v-vmin, where (u,v) is the target address output by the TMC2302A. in the three-dimensional mode, the x/u transformation equa- tion is: x = a + bu + ev + kw + fuv + ivw + luw + juvw see ?he image transformation polynomial?section of the applications discussion. figure 1. image resampling geometry showing two-dimensional image rotation and expansion (xmin, ymin) original (source) image new (target) image note 2 note 1 new pixel x y (umin, vmin) (xmax, ymax) (u 0 , v 0 ) (umax, vmax) 65-2302-03 u v notes: 1. coordinate transformation u, v pixel mapped into x, y coordinates. 2. bilinear pixel interpolation walk. new u, v pixel intensity calculated from surrounding x, y pixel neigborhood.
TMC2302A product specification 4 preliminary information figure 2. basic two-dimensional image convolver using TMC2302A ims with typical 8-bit data path 16 16 16 8 8 8 8 8 x 16 2 x 16 2 x 24 source address destination address idat 15-0 idar 6-0 acc wr x, y, p y idar 6-0 data in kadr 7-0 , sadr 7-0 sadr 7-0 idat 15-0 TMC2302A row (x) TMC2302A row (y) source image buffer ram multiplier- accumulator destination image buffer ram image data out 65-2302-04 image data in address address interpolation coefficient buffer ram tadr 11-0 tadr 11-0 twr data out acc sadr 23-8 sadr 23-8 initialization data control clock clock the TMC2302A utilizes an external multiplier-accumulator or interpolator, connected to the system clock, to calculate the interpolated pixel value for each color. the products of the original source image pixel values surrounding the remapped pixel location (interpolation kernel) and the appro- priate weights stored in the coef?ient lookup table are summed. the resulting new interpolated image pixel value is then stored in the corresponding (u, v, w) memory location in the target image memory buffer. next, the target image address is incremented by one in the ??direction until umax is reached (end of line), when u is reset to umin, and the v counter is incremented to give the ?st pixel loca- tion in the next line. the process is repeated, proceeding line-by-line through the image, until vmax is reached. in the case of three-dimensional images, the ims system also steps through each page in the image, incrementing in the ??direction with the completion of each image plane until wmax is reached, and the transformation is complete. the image manipulation sequencer can support any nearest- neighbor, bilinear interpolation, or cubic convolution resam- pling. interpolation kernels of more than one pixel require an external interpolation coef?ient lookup table and multiplier- accumulator or multiple multiplier array. one, two, and three-pass algorithms are supported. for each output point in a typical two-dimensional single-pass static image ?ter, the TMC2302A implements a spiralling pixel resampling algo- rithm, ?alking?around the resampling neighborhood in two dimensions and generating the appropriate coef?ient table addresses to sum up the interpolated pixel value in the external pixel interpolator. at the end of each walk, the TMC2302A will advance one pixel along the output scan line and then execute the walk for that next pixel. when per- forming multiple-pass interpolation, the TMC2302A system proceeds along only one dimension per pass, which requires dimensionally separable, preferably orthogonal, coef?ients. a basic, two-dimensional TMC2302A-based system is shown in figure 2 . in this typical arrangement, two image manipulation sequencers process the image. the only other components needed beyond the source and target image buffer memories are a multiplier-accumulator or pixel inter- polator such as the tmc2246a image mixer or tmc2250a matrix multiplier, and the interpolation coef?ient lookup table ram or rom.
product specification TMC2302A 5 preliminary information pin assignments 120 pin plastic pin grid array, ppga b a d e f g h j k l m n c 12345678910111213 top view cavity up key 65-2302-05 gnd sadr 16 sadr 17 v dd sadr 21 oes iadr 6 iadr 3 iadr 0 idat 15 idat 12 idat 9 v dd sadr 14 sadr 15 v dd sadr 18 sadr 20 sadr 23 iadr 4 iadr 2 ics idat 13 idat 11 idat 8 idat 7 sadr 13 v dd v dd gnd a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 c1 c2 c3 c4 sadr 19 sadr 22 iadr 5 iadr 1 idat 14 idat 10 gnd gnd idat 6 sadr 11 sadr 12 gnd v dd idat 5 idat 4 sadr 9 sadr 10 gnd gnd idat 3 idat 2 sadr 7 sadr 8 v dd v dd gnd idat 1 sadr 6 gnd v dd c5 c6 c7 c8 c9 c10 c11 c12 c13 d1 d2 d3 d11 d12 d13 e1 e2 e3 e11 e12 e13 f1 f2 f3 f11 f12 f13 g1 g2 g3 pin name pin name gnd v dd idat 0 sadr 5 sadr 4 gnd gnd v dd sync sadr 3 sadr 2 v dd v dd clk iwr sadr 1 sadr 0 gnd v dd init gnd sval v dd nc v dd gnd kadr 0 v dd tadr 4 tadr 8 g11 g12 g13 h1 h2 h3 h11 h12 h13 j1 j2 j3 j11 j12 j13 k1 k2 k3 k11 k12 k13 l1 l2 l3 l4 l5 l6 l7 l8 l9 done v dd gnd noop acc oek kadr 6 kadr 4 kadr 2 oet tadr 0 tadr 3 tadr 6 tadr 9 gnd gnd tval gnd kadr 7 kadr 5 kadr 3 kadr 1 twr tadr 1 tadr 2 tadr 5 tadr 7 tadr 10 tadr 11 endd l10 l11 l12 l13 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 pin name pin name
TMC2302A product specification 6 preliminary information pin assignments (continued) 120 lead metric quad flat pack, mqfp pin descriptions pin name pin number pin function description ppga mqfp power v dd c3, c2, f3, g3, j3, l2, l4, l7, l11, k11, j11, h12, g12, f11, d11, a13, a4, b3 1, 5, 12, 16, 24, 29, 33, 45, 61, 64, 68, 73, 75, 80, 88, 90, 113, 119 supply voltage. the TMC2302A operates from a single +5v supply. all pins must be connected. gnd d3, e3, g2, h3, k3, n1, l5, m11, m12, l12, k13, h11, g11, f12, e11, c12, c11, c4, a1 4, 8, 15, 20, 28, 30, 37, 58, 62, 65, 69, 72, 76, 79, 84, 89, 91, 118, 120 ground. v dd sadr 15 sadr 14 gnd v dd sadr 13 sadr 12 gnd sadr 11 sadr 10 sadr 9 v dd sadr 8 sadr 7 gnd v dd sadr 6 sadr 5 sadr 4 gnd sadr 3 sadr 2 sadr 1 v dd sadr 0 sval acc gnd v dd gnd 1 30 120 91 31 60 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 61 oek kadr 7 v dd kadr 6 kadr 5 kadr 4 gnd kadr 3 kadr 2 kadr 1 kadr 0 oet twr tadr 0 v dd tadr 1 tadr 2 tadr 3 tadr 4 tadr 5 tadr 6 tadr 7 tadr 8 tadr 9 tadr 10 tadr 11 done gnd nc endd 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 65-2302-06 pin name pin name v dd gnd tval v dd gnd noop init v dd gnd clk iwr gnd v dd sync v dd gnd idat 0 idat 1 gnd v dd idat 2 idat 3 idat 4 gnd idat 5 idat 6 idat 7 v dd gnd v dd 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 gnd idat 8 idat 9 idat 10 idat 11 idat 12 idat 13 idat 14 idat 15 ics iadr 0 iadr 1 iadr 2 iadr 3 iadr 4 iadr 5 iadr 6 oes sadr 23 sadr 22 sadr 21 sadr 20 v dd sadr 19 sadr 18 sadr 17 sadr 16 gnd v dd gnd 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 pin name pin name
product specification TMC2302A 7 preliminary information clocks clk j12 70 system clock . the pixel clock of the TMC2302A strobes all internal registers except the control parameter preload registers. all timing specifications except those are referenced to the rising edge of clk. iwr j13 71 input parameter write clock. the internal image transformation and configuration control parameter registers are double buffered to simplify interfacing with system controllers. depending on the state of the chip selects ics , control words input to idat 15-0 and the corresponding addresses presented to iadr 6-0 are strobed into the outer preload registers on the rising edge of the input parameter write clock iwr . the last parameter must be loaded twice on two consecutive rising edges of iwr . inputs idat 15-0 a10, c9, b10, a11, b11, c10, a12, b12, b13, c13, d12, d13, e12, e13, f13, g13 99, 98, 97, 96, 95, 94, 93, 92, 87, 86, 85, 83, 82, 81, 78, 77 input parameter data. configuration and transformation parameter input data are presented, along with the appropriate input register address word iadr 6-0 , to the parameter input data port, and are latched into the preload registers on the next rising edge of iwr . preload register updates are disabled by the chip select control ics . see figure 3. iadr 6-0 a7, c7, b7, a8, b8, c8, a9 107, 106, 105, 104, 103, 102, 101 input parameter address. the input parameter preload register currently indicated by the input parameter register address iadr 6-0 is loaded with the data presented to input port idat on the rising edge of iwr , as demonstrated in figure 3. outputs sadr 23-0 b6, c6, a5, b5, c5, b4, a3, a2, b2, b1, c1, d2, d1, e2, e1, f2, f1, g1. h1, h2, j1, j2, k1, k2 109, 110, 111, 112, 114, 115, 116, 117, 2, 3, 6, 7, 9, 10, 11, 13, 14, 17, 18, 19, 21, 22, 23, 25 source address. the 24-bit address of one dimension (x, y, z) of the source image pixel value currently being resampled is output through the source address port sadr 23-0 . this port can be forced to the high-impedance state by the enable control oes . kadr 7-0 n2, m3, n3, m4, n4, m5, n5, l6 32, 34, 35, 36, 38, 39, 40, 41 coefficient address. the integer address steps for each dimension of the spiral interpolation walk performed by the TMC2302A, as determined by the transform parameter kernel, are generated by the internal walk counter and output at the coefficient address output port kadr 7-0 . this port can be forced to the high-impedance state by the enable control oek . pin descriptions (continued) pin name pin number pin function description ppga mqfp
TMC2302A product specification 8 preliminary information tadr 11-0 n12, n11, m10, l9, n10, m9, n9, l8, m8, n8, n7, m7 56, 55, 54, 53, 52, 51, 50, 49, 48, 47, 46, 44 target address. the 12-bit address of one dimension (u, v, w) of the target image pixel value just resampled is output through the target address port tadr 11-0 . this port is forced into the high- impedance state by the enable control oet . tadr 11-0 can be delayed up to seven clock cycles after the nominal sequence shown in table 4 by utilization of the pipeline delay parameter piptad. for systems requiring greater spatial resolution in the source image than that offered by the sadr 23-0 alone, the target address port can be reconfigured to output 12 additional lsbs of the source address by placing the device into the extended mode, in which case the pipeline delay parameter must be set to 0 to maintain alignment with the current source address port output. see the device configuration and control parameters section. controls init k12 67 initialize. the TMC2302A control logic is cleared and initialized for the start of a new image transformation, and the internal working registers are updated with the contents of the current control parameter preload registers when the registered control input init is high. the image transformation then commences with the first source image pixel address nine clocks after init is returned low. sync h13 74 run/halt. the user can select between continuous or one-frame operation with the registered input control sync. assuming that init remains low and noop remains high, if sync remains high at the end of a transform the TMC2302A will begin the next image transformation without interruption. this assumes either that the user is not changing the parameter set, or that a new set of parameters has already been loaded into the preload registers midframe, prior to the beginning of the last line in the transform. if sync is low during the last clock cycle of a transform, the device will complete the image, having loaded the new transform parameter set during the first clock of the final line of the transform, and halt in the state set on the first clock cycle of the next transform. these outputs are held until sync is again brought high, and operation resumes on the next clock. see figure 5. ics b9 100 input parameter chip select. the input parameter preload register write clock iwr , and thus the preloading of all configuration and transformation parameters, is disabled on the next clock when the registered input parameter chip select input is high. when ics returns low, they are enabled on the next clock. see figure 3 . acc m1 27 accumulate. the external pixel interpolator or multiplier- accumulator is initialized for a new accumulation of products by the registered accumulator control output acc. on the first cycle of each interpolation walk, this output goes low for one cycle, effectively clearing the register by loading in only the first new resampled pixel value. when performing nearest-neighbor resampling, this control will remain low throughout the entire transform. this output can be delayed up to seven clock cycles after the nominal sequence shown in table 4 by the pipeline delay parameter pipacc. see the device configuration and control parameters section. pin descriptions (continued) pin name pin number pin function description ppga mqfp
product specification TMC2302A 9 preliminary information twr n6 43 target memory write enable. on the last cycle of each interpolation walk, the target write enable goes low for one clock cycle, returning high for all but the last cycle of the next walk. when performing nearest-neighbor resampling, this control will remain low throughout the entire transform. this output can be forced to the high-impedance state by the enable control oet , and can be delayed up to seven clock cycles after the nominal sequence shown in table 4 by the pipe-line delay parameter piptwr. see the device configuration and control parameters section. noop l13 66 no operation. assuming that init remains low, the internal system clock of the TMC2302A will be disabled on the next clock, halting the current transform, when the registered control input noop goes low. when noop returns high, normal operation resumes on the next clock. this control does not affect the loading of the configuration and transformation parameter preread registers. oes a6 108 source address output enable. the source address port sadr 23-0 is enabled when the asynchronous output enable oes is low. when oes is high, the port is in the high-impedance state. oek m2 31 coefficient address output enable. the interpolation coefficient address port kadr 7-0 is enabled when the asynchro- nous output enable oek is low. when oek is high, the port is in the high- impedance state. oet m6 42 target address output enable. the target address port tadr 11- 0 and target write enable twr are enabled when the asynchronous target output enable oet is low. when oet is high, these outputs are in the high-impedance state. this control functions in both the normal and extended addressing modes. flags sval l1 26 source address valid. when the current source image address component output is within the working space defined by the parameters xmin and xmax (or ymin, ymax for the column (y/v) device or zmin, zmax for the page (z/w) device), the source address valid flag sval for that device is low. this flag will go high on the clock in which the corresponding component address falls outside the defined region. in a typical system, the sval outputs of all ims devices are or?d together to generate a global boundary violation flag. the user might then insert zeroes into the pixel interpolator to ignore that portion of the image outside the defined space, or insert a background color or image. this output can be delayed up to seven clock cycles after the nominal sequence shown in table 4 by the pipeline delay parameter pipsva. see the device configuration and control parameters section. pin descriptions (continued) pin name pin number pin function description ppga mqfp
TMC2302A product specification 10 preliminary information tval m13 63 target address valid. when the current target image addresses are within the working space defined by the parameters umini and umaxi, and vmini and vmaxi (and wmini and wmaxi for systems processing three-dimensional images), the target address valid flag tval for that device is low. this flag will go high on the clock in which the current target address outputs fall outside the defined region, which must fall inside the target area defined by umin, umax, etc. since each TMC2302A device is programmed with distinct mini/maxi parameters and generates a separate tval flag, the user may define separate two or three- dimensional target space windows for each device. tval can be delayed up to seven clock cycles after the nominal sequence shown in table 4 by the pipeline delay parameter piptva. see the device configuration and control parameters section. endd n13 60 end of dimension. during the last pixel interpolation walk of a row (x/u device), the last row in a page (y/v device), or the last page in a three-dimensional transform (z/w device), the flag endd goes high for the entire walk, indicating end of the transform in that dimension. it remains low otherwise. this output can be delayed up to seven clock cycles after the nominal sequence shown in table 4 by the pipeline delay parameter pipend. see the device configuration and control parameters section. done l10 57 done. on the last clock cycle of the current image transform, the done flags on all TMC2302As go high for one clock cycle. on the next clock cycle, all devices output the first addresses and control signals for the next image transform. if sync is low, the ims system halts. if sync is high, operation continues without interruption. see ?ync,?in the controls section. this flag can be delayed up to seven clock cycles after the nominal sequence shown in table 4 by the pipeline delay parameter pipdon. also see ?fls,?in the device configuration and control parameters section. no connects nc l3 59 no connect. d4 index pin. pin descriptions (continued) pin name pin number pin function description ppga mqfp
product specification TMC2302A 11 preliminary information transformation coef?ient and con?uration and control parameters the TMC2302A is intended to act as a co-processor, requir- ing only that the user program the device to perform the image transformation desired by loading in the appropriate device con?uration and transformation control parameters discussed in this section. the user then issues an ?nit? command, allowing his system to run unattended until the completion of the image when a ?one??g is generated to inform the host system. the capabilities and ?xibility of the TMC2302A image manipulation sequencer are apparent when reviewing the following tables which de?e the transformation coef?ient and con?uration and control parameters. these tables are broken up into two separate groups. the ?st parameters dis- cussed are the control words which select the dimension cal- culated, the functional con?uration of each device, the working space in which they will operate, the size of the interpolation kernel desired, and the timing of the various address and control signals involved in handling the pixel data pipeline. the second parameters are the polynomial transform coef?ients used in performing image manipula- tion. the TMC2302A utilizes three levels of internal 48-bit accumulators to calculate these values by forward difference accumulation, generating no signi?ant cumulative spatial error for most applications. the user must be aware that all internal parameter and coef?ient registers must be set by the user, including resetting after powerup any unused con- trol words or coef?ients. as mentioned above, the TMC2302A also features user- programmable image data pipeline con?uration controls. all output signals except the source and coef?ient address outputs can be individually delayed by the user up to seven clocks after the nominal system timing illustrated in table 4. this allows the user to software-con?ure the TMC2302As in his system to match his pixel interpolator, image buffer, and interpolation coef?ient ram structure timing. the user can also program the device to continue into the next image for a set number of clock cycles after the done ?g has appeared. first, this ushes?the ?al resampled pixel data word through the interpolation pipeline, all the way to the target image ram. also, valid pixel data will then appear on the ?st clock of the next transform indepen- dent of the length of the pixel pipeline, incurring no lost clock cycles. device con?uration and control parameters note: the parameter umax must exceed umin so as to ensure that a minimum of 5 system clock cycles in two- dimensional operation, or 15 clock cycles in three-dimen- sional operation, pass between the periods in which these two target address values are generated. thus in 2d nearest neighbor operation umax must be 5 greater than umin. in 2d bilinear interpolation mode (4-pixel two-dimensional kernel) the distance must be two pixels in the target image (actually enforcing a spacing of 8 system clocks). umin, vmin, wmin the memory addresses of the target image boundaries corresponding to the top, left side, and front page of the new image being gener- ated are de?ed in all devices of the user's system by the parameters umin, vmin, and wmin, respectively. at the beginning of the transformation, the initial source image coor- dinate (x 0 , y 0 , z 0 ) will be mapped to this coordinate set. the numeric format assumed is 12-bit unsigned binary integer. umax, vmax, wmax the memory addresses of the target image boundaries corresponding to the bottom, right side, and last page of the image being generated are de?ed in all devices by the parameters umax, vmax, and wmax, respectively. these values should be greater than the umin/vmin/wmin values de?ed above. numeric format assumed is unsigned 12-bit binary integer. umini, vmini, wmini the target image addresses corresponding to those of the top, left side, and front page of the 2 or 3 dimensional region indicated by the valid target address ?g tv al are umini, vmini, and wmini, respectively. thus, to de?e a valid region beginning at ?,?the mini parameter value is ?,?these parame- ters are assumed to be in 12-bit unsigned binary integer format. proper tval operation requires umin < umini < umaxi < umax, etc. umaxi, vmaxi, wmaxi the target image addresses one more than those of the right side, bottom and back page of the region indicated by the valid target address ?g tv al are umaxi, vmaxi, and wmaxi, respectively. thus, to de?e a valid region ending at ?,?the maxi parameter value is ?+1? these parameters are assumed to be in 12-bit unsigned integer format.
TMC2302A product specification 12 preliminary information xmin, xmax the source image boundaries are de?ed for each device by the parameters xmin and xmax, in the case of the row device. the column device then contains ymin and ymax, and the page device (in systems performing three-dimensional operations) zmin and zmax. the value of xmax should be greater than xmin if the boundary violation ?g sv al is to operate correctly. these values are assumed to be in 32-bit unsigned binary integer format. pfls the user can set the number of clock cycles that the TMC2302A continues in to the next image following the done ?g, allowing his system to flush all control and data pipeline paths and halt after a maximum of seven cycles. the numeric format assumed is three- bit unsigned binary integer. ptad, pdon, pend, ptva, psva, ptwr, pacc as mentioned above, the control signals and target image pixel addresses generated by the TMC2302A can be delayed up to seven clock cycles after the nominal timing shown in table 4 by setting the appropriate pipeline delay word. the numeric format assumed for all delay words is three-bit unsigned binary integer. xtnd when the user sets the control bit xtnd to 1, the TMC2302A operates in an extended- resolution source address bus con?uration. assuming that the user has his own raster scan generator available elsewhere to manage the ?w of output pixels from the TMC2302A system, the target address output bus tadr 11-0 is recon?ured internally into an extension of the source address bus, as sadr 11-0 . the original source address bus sadr 23-0 is then sadr 35-12 , providing 36 bits of spatial reso- lution in the source address space. an xtnd of 0 puts the device in the standard 24-bit source, 12-bit target address con?uration. e3d setting this control bit to 0 indicates a two-dimensional image transform is to be performed. when the e3d is set to 1, a three- dimensional image is assumed, using three TMC2302A devices. dim the user sets each TMC2302A to operate in a speci? dimension as follows: dim 1,0 dimension 00 x/u (row) device 01 y/v (column) device 10 z/w (page) device 11 no operation mode in systems performing the standard two-dimen- sional spiral interpolation walk, mode is set to 11, indicating single-pass operation. when performing multiple-pass resampling, the user must set this two-bit control word pass-by-pass in all imss, to implement each pass direction. for instance, setting mode to 00 causes the TMC2302A system to increment only in the x-direction, holding the y (and z) addresses constant until the end of that pixel walk. on the next pass through the image, the user sets mode = 01, with the kernel increment in y only. in 3d, the ims system then proceeds again through the (u, v) target image space, walking kernels only along the z direction. mode 1,0 resampling performed 00 x-pass 01 y-pass 10 z-pass 11 two-dimension spiral walk kernel this parameter determines the size of the inter- polation walk performed. to implement a convolutional sum of k+1 pixels, the parameter kernel is set to k, up to a maximum of 255. in single-pass operation, this value must be identical in all devices, giving a square interpo- lation kernel. in multiple-pass operation, how- ever, non- square kernels may be implemented, with different k values in each dimension. or, the user could utilize a banded memory architec- ture in two-pass mode to access an entire row or column of a kernel in one clock, completing the entire sum in a single pass through the other dimension of the kernel. numeric format is 8-bit unsigned integer. fov the user determines the size of each step in an interpolation walk, in terms of the number of source image pixels, by setting the field of view control. the binary weighting of the image transformation parameters and source address must be taken into account when determining this value. see table 6 and the applications discussion section. the numeric format assumed is unsigned 16-bit integer.
product specification TMC2302A 13 preliminary information table 1. control parameter registers binary format (row, column or page device) addr format limits name hex msb lsb dec hex umin 30 2 1 1 2 1 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 4095 0 fff 000 umax 31 2 1 1 2 1 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 4095 0 fff 000 umini 32 2 1 1 2 1 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 4095 0 fff 000 umaxi 33 2 1 1 2 1 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 4095 0 fff 000 vmin 34 2 1 1 2 1 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 4095 0 fff 000 vmax 35 2 1 1 2 1 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 4095 0 fff 000 vmini 36 2 1 1 2 1 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 4095 0 fff 000 vmaxi 37 2 1 1 2 1 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 4095 0 fff 000 wmin 38 2 1 1 2 1 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 4095 0 fff 000 wmax 39 2 1 1 2 1 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 4095 0 fff 000 wmini 3a 2 1 1 2 1 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 4095 0 fff 000 wmaxi 3b 2 1 1 2 1 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 4095 0 fff 000 xminl 3c 2 1 5 2 1 4 2 1 3 2 1 2 2 1 1 2 1 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 0 00000000 xminm 3d 2 3 1 2 3 0 2 2 9 2 2 8 2 2 7 2 2 6 2 2 5 2 2 4 2 2 3 2 2 2 2 21 2 20 2 19 2 18 2 17 2 16 2 32 -1 ffffffff xmaxl 3e 2 1 5 2 1 4 2 1 3 2 1 2 2 1 1 2 1 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 0 00000000 xmaxm 3f 2 3 1 2 3 0 2 2 9 2 2 8 2 2 7 2 2 6 2 2 5 2 2 4 2 2 3 2 2 2 2 21 2 20 2 19 2 18 2 17 2 16 2 32 -1 ffffffff pfls 40 2 2 2 1 2 0 7 0 7 0 ptad 40 2 2 2 1 2 0 7 0 7 0 pdon 40 2 2 2 1 2 0 7 0 7 0 pend 40 2 2 2 1 2 0 7 0 7 0 ptva 40 2 2 2 1 2 0 7 0 7 0 psva 41 2 2 2 1 2 0 7 0 7 0 ptwr 41 2 2 2 1 2 0 7 0 7 0 pacc 41 2 2 2 1 2 0 7 0 7 0 xtnd 41 xtnd e3d 41 e3d dim 41 dim 1 dim 0 mode 41 mode 1 mode 0 kernel 42 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 255 0 ff 00 fov 43 2 1 5 2 1 4 2 1 3 2 1 2 2 1 1 2 1 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 16 -1 0 ffff 0000
TMC2302A product specification 14 preliminary information transformation parameter registers the transformation parameter word storage register addresses for the x/u device are listed in table 2, along with the differential terms for each polynomial coef?ient for both two and three-dimensional transforms. the polynomial terms for the other ims device(s) are found by replacing every ??in the table with a y (or z). a TMC2302A-based system can perform image manipulations of up to third order in two dimensions, and three-dimensional transforms of up to order 1.5 (rst-and-a-half order?. also, see ?he image transformation polynomial? in the applications discussion section. the notation used to de?e each polynomial coef?ient term in table 2 is easily interpreted. each differential is of course de?ed by a differential in x, followed by the corresponding dependent u, v, or w terms. thus, dxuv is equivalent to d 2 x/dudv and dxuuuv to d 4 x/du 3 dv. table 2. transformation polynomial coef?ient register addresses note: 1. the x 0 and dxu terms must each be loaded into two different registers when performing 3d transforms. table 2 shows the binary weighting of all of the transformation parameter words, which are 48-bit signed fractional binary. table 3. integer binary weighting of transformation parameters note: 1. a minus sign indicates a sign bit. name parameter coef?ient word addresses (hex) 2d term 3d term msw csw lsw ax 0 x 0 00 01 02 b dxu dxu 03 04 05 c dxuu 06 07 08 d dxuuu 09 0a 0b e dxv dxv 0c 0d 0e f dxuv dxuv 0f 10 11 g dxuuv x 0 12 13 14 h dxuuuv dxu 15 16 17 i dxvv dxvw 18 19 1a j dxuvv dxuvw 1b 1c 1d k dxuuvv dxw 1e 1f 20 l dxuuuvv dxuw 21 22 23 m dxvvv 24 25 26 n dxuvvv 27 28 29 o dxuuvvv 2a 2b 2c p dxuuuvvv 2d 2e 2f format limits msb lsb dec hex msb -2 47 2 46 2 45 2 44 2 43 2 42 2 41 2 40 2 39 2 38 2 37 2 36 2 35 2 34 2 33 2 32 2 48 -1 ffffffffffff csw 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 lsw 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 0 000000000000
product specification TMC2302A 15 preliminary information figure 3. image transformation and configuration control parameters register structure figure 3 depicts the control preload register structure and figure 4b gives the corresponding timing relationships. table 4. nominal output signal timing note: 1. kadr 7-0 timing identical. sadr 23-0 1 acc tadr 11-0 twr end done x i-1,j,0 0u l-1,m 100 x i-1,j,1 1u l-1,m 100 x i-1,j,2 1u l-1,m 100 x i-1,j,k 1u l-1,m 010 x i,j,0 0u l,m 110 x i,j,1 1u l,m 110 x i,j,2 1u l,m 110 x i,j,k 1u l,m 011 68 (a) internal logic. registers are enabled for the start of each new transition or by init high. 16 TMC2302A to rest of chip internal register preload register de- code 7 pixel clock idat 15-0 65-2302-07 iwr ics clk init sync iadr 6-0 en en (a) the nominal sequence of address and control signals of a two-dimensional, single-pass-programmed TMC2302A system, with all pipe parameters set to 0, is shown in table 4. here, the values of the last two new target image pixels u l-l,m and u l,m are being calculated, and the begin- ning and end of the interpolation walks of length k which sample source image pixels in the neighborhod of locations (x i-1,j , x i,j ) can be seen. utilizing the arrival of the source image address (sadr 31-0 ) as a reference point, the other signals shown can be delayed up to seven clock cycles from the nominal timing shown here, allowing the user to con?- ure these outputs to match the timing latencies of his pixel data path structure. considerable speed and timing variations in image buffer memory, data register, and pixel interpolator structure can thus be accomodated, with minimal corre- sponding support hardware. also see ?fls,?in the device con?uration and control parameters section.
TMC2302A product specification 16 preliminary information equivalent circuits and threshold levels figure 5. equivalent input circuit figure 6. equivalent output circuit figure 7. threshold levels for three-state measurements absolute maximum ratings (beyond which the device may be damaged) 1 notes: 1. absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. functional operation under any of these conditions is not implied. parameter min. max. units supply voltage -0.5 + 7.0 v input voltage -0.5 v dd + 0.5 v output applied voltage -0.5 v dd + 0.5 v short-circuit duration (single output in high state to ground) 1 second operating, case temperature -60 130 c junction temperature 175 c lead, soldering temperature (10 seconds) 300 storage temperature -65 +150 c v dd p 65-2302-08 p+ n+ d1 d2 1k ? gnd n substrate control input p well v dd p n p+ n+ d1 d2 gnd n substrate 65-2302-09 p well 65-2302-10 t ena 2.0v 0.8v t dis three-state outputs oes, oek, oet 0.5v 0.5v high impedance
product specification TMC2302A 17 preliminary information operating conditions electrical characteristics 1 note: 1. actual test conditions may vary from those shown, but guarantee operation as specified. parameter test conditions -1 units min. nom. max. min. nom. max. v dd supply voltage 4.75 5.0 5.25 4.75 5.0 5.5 v v il input voltage, logic low 0.8 0.8 v v ih input voltage, logic high 2.0 2.0 v l ol output current, logic low 8.0 8.0 ma i oh output current, logic high -4.0 -4.0 ma t cy cycle time v dd = min 33 25 ns t pwl clock pulse width, low v dd = min 15 12.5 ns t pwh clock pulse width, high v dd = min 15 10 ns t s input setup time 10 8 ns t h input hold time 2 2 ns t a ambient temperature, still air 0 70 0 70 c parameter test conditions min. max. units i ddq supply current quiescent v dd = max, v in = 0v 10 ma i ddu supply current, unloaded v dd = max, f = 20mhz, oes = oek = oet = 5v 70 ma i il input current, logic low v dd = max, v in = 0v -10 m a i ih input current, logic high v dd = max, v in = v dd 10 m a v ol output voltage, logic low v dd = min, i ol = max 0.4 v v oh output voltage, logic high v dd = min, i oh = max 2.4 v i ozl high-z output leakage current, output low v dd = max, v in = 0v -40 m a i ozh hi-z output leakage current, output high v dd = max, v in = v dd 40 m a i os short-circuit output current v dd = max, output high, one pin to ground, one second duration max. -20 -70 ma c i input capacitance t a = 25 c, f = 1mhz 10 pf c o output capacitance t a = 25 c, f = 1mhz 10 pf
TMC2302A product specification 18 preliminary information switching characteristics note: 1. all transitions are measured at a 1.5v level except for t dis and t ema . timing diagrams figure 4a. timing diagram, figure 4b. timing diagram, preload parameters pixel clock, control, and outputs parameter -1 test conditions min. max. min. max. units t do output delay v dd = min, c load = 25pf 15 12 ns t ho output hold time v dd = max, c load = 25pf 4 4 ns t ena three-state output enable delay 1 v dd = min, c load = 25pf 12 12 ns t dis three-state output disable delay 1 v dd = min, c load = 25pf 15 15 ns clk inputs 1 outputs 2 t cy t s t h t d t ho valid 65-2302-11 valid t pwl t pwh notes: 1. except oes, oet, and oek. 2. assumes oes, oet, and oek = low. all pipeline latency parameters set to 0. dat 1 adr 1 iwr idat iadr ics t s t h t pwl 65-2302-12 value "dat 1" is loaded into address "adr 1" on the second rising edge of iwr, since ics = 0, having been acquired by the input register on the first edge. applications discussion the image transformation polynomial on any given clock cycle, when performing a two-dimen- sional geometric transformation the addresses output by the row (x/u) TMC2302A are generated by forward difference accumulation according to the following third-order polyno- mial: x(u,v) = a + bu + cu 2 +du 3 + ev + fvu + gvu 2 + hvu 3 + iv 2 + jv 2 u + kv 2 u 2 + iv 2 u 3 + mv 3 + nv 3 u + ov 3 u 2 + pv 3 u 3 + fov ?cax(ca) the polynomial utilized for three-dimensional transforms is: x(u,v,w) = a + bu + ev + kw + fuv + ivw + luw + juvw + fov ?cax (ca) where 0 u umax-umin, 0 v vmax-vmin, 0 w wmax-wmin, and the polynomials for the column or page devices are obtained by replacing the x by a y or z, as appropriate.
product specification TMC2302A 19 preliminary information fov is the 16-bit ?ld-of-view parameter, normally set so that the spiral walk proceeds in single-pixel steps. fov can be increased to expand the step size and thus the spiral walk, subsampling the image. see table 1 and table 6. also, cax(ca) is the current value of the coef?ient address. see the interpolation coef?ient lookup table addressing. if the spiral walk isnt used, cax = 0 and fov is ignored. we can reform the two-dimensional polynomial as: x(u,v) = (a + ev + iv 2 + mv 3 ) + (b + fv + jv 2 + nv 3 )u + (c + gv + kv 2 + ov 3 )u 2 + (d + hv + iv 2 + pv 3 )u 3 , and retain the simpler three-dimensional form: x(u, v, w) = a + bu + ev + kw + fuv + ivw + luw + juvw and de?e each of the polynomial coef?ients in arithmetic terms as shown in table 5. table 5. transformation polynomial coef?ients parameter two-dimensional three-dimensional name term coef?ient term coef?ient ax 0 ax 0 a b dxu b + c + d dxu b c dxuu 2c + 6d 0 d dxuuu 6d 0 e dxv e + i + m dxv e f dxuv f + g + h + j + k + i + n + o + p dxuv f g dxuuv 2(g + k + o) + 6(h + i +p) x 0 a h dxuuuv 6(h + i + p) dxu b i dxvv 2i + 6m dxvw i j dxuvv 2(j + k + i) + 6(n + o + p) dxuvw j k dxuuvv 4k + 12i + 12o + 36p dxw k l dxuuuvv 12i + 36p dxuw i m dxvvv 6m 0 n dxuvvv 6(n + o + p) 0 o dxuuvvv 12o + 36p 0 p dxuuuvvv 36p 0 understanding the polynomial coef?ients an overview as the formulae indicate, the source address is a polynomial function of the two (or three) dimensions of the target address. each of the 16 terms of the equation is of the form: and may be treated approximately as a mixed partial difference of order m, n, and p. d mnp ++ x du m dv n dw p ------------------------------- - the simplest term, x 0 , is a zeroeth (non-) function of the target addresses; it speci?s the source address point corre- sponding to the upper left point in the target space. x 0 generates image translation or ?an. the next-simplest terms, dx/du and dy/dv, govern the rela- tive scales of the source and target images, i.e., how large a step in source space corresponds to a unit step in the corre- sponding direction in the target space. as long as the cross- terms, dx/dv and dy/du, are zero, this is a straight scale (?oom? operation, without rotation or shear.
TMC2302A product specification 20 preliminary information the ?st-order cross terms, dx/dv and dy/du, generate source space displacements perpendicular to unit displace- ments in the target space, thereby causing shearing of the image. in conjunction with the parallel source terms described above, they govern rotation, shear, and scaling of the image. although the actions of the higher-order terms become pro- gressively dif?ult to describe, all terms behave essentially as partial differences of various orders, and a little thought and common sense will generally lead the user to the proper conclusions. for example, the term dxuu (using the nota- tion of table 2) is a horizontal scale factor which increases as one progresses across each row, causing a quadratic horizon- tal warp. in fact, all terms of the form d m x/du m or d n y/dv n cause only stretching of the image, never rotation. interpolation coef?ient lookup table addressing the external coef?ient lookup table ram stores the inter- polation coef?ient values used to calculate the value of the new pixel. these values are selected by the user, allowing maximum ?tering ?xibility. in simple ?tering applica- tions, the source and target pixel addresses map one-to-one, and only one interpolation coef?ient set is required. these integer addresses are generated for each dimension by the internal walk counters of each TMC2302A. however, applications performing a coordinate transforma- tion will almost always generate non-integer source pixel addresses; that is, the u (or v) locations will not map to the x (or y) addresses exactly, and a fractional source address components are generated. the user must then expand the interpolation coef?ient lookup table to include spatially- corrected values, as detemnined by the subpixel resolution of the system. the tmc2301 image resampling sequencer allows the user to trade subpixel resolution against interpolation step size by obtaining the interpolation coef?ient addresses directly from the fractional part of the source address. the TMC2302A gives the user 16 different interpolation bit weighting positions. the complete interpolation coef?ient address for that dimension then consists of both the 8-bit interpolation walk address kadr 7-0 , weighted to match the source address binary point by the parameter fov, and the fractional portion of the source pixel address sadr 23-0 , to the desired subpixel resolution. see table 6. internal and external data formats the source address value output by the TMC2302A is a 24-bit two's complement number, with binary point assign- able by the user anywhere in the 16 lower bits. the extended mode appends 12 additional fractional bits for greater output precision. all internal computations include these 24 plus 12 bits, plus an additional 12 lower bits, for 48-bit precision. see table 6. intemally, each TMC2302A's source address (x, y,or z) generator computes a 48-bit address through a mode-speci? accumulation of the sixteen 48-bit user-speci?d resampling parameters. the 24 most signi?ant bits of the ?al accumu- lation emerge via the source address port whereas the "extend" mode makes the 12 next most-signi?ant bits avail- able at the target address port. the 12 least signi?ant bits are truncated internally. source address bit weighting and setting the binary point when performing nearest-neighbor resampling, the user may arbitrarily trade source image size against subpixel resolu- tion merely by adhering to a single binary point position for all resampling parameters. for example, if the binary point follows the 16 most signi?ant bits in each resampling parameter, then it will appear following the source address?6 most signi?ant bits, leaving 8 (20 in extended mode) bits of subpixel resolution on sadr n . since the TMC2302A has no internal limiter, the user should select the source address weighting appropriately. moving the source address connections to the right and reducing the resampling parameters accordingly, reduces the chance of arithmetic over?w while increasing arithmetic round-error. in any ?tering or resampling operation performing an inter- polation walk, the user should set the field or view (fov) parameter according to the desired binary point position determined above, as follows. to provide 2 24 integral pixel positions per dimension, with no subpixel resolution, set fov = 001 (hex). for 2 23 positions with 1-bit (0,5) subpixel resolution, fov = 0010 (hex). similarly, for 2 9 positions and 15-bit subpixel resolution. fov = 8000 (hex). as shown in table 6, using the parameter fov the user effectively ?hifts?the bit weight of the coef?ient address word kadr 7-0 to match the established location of his source address binary point. in each case, the extend mode provides 12 additional bits of subpixel resolution but eliminates the separate target or raster address, which must then be generated elsewhere in the user's system.
product specification TMC2302A 21 preliminary information table 6. relative bit weighting ?source address note: 1. a minus sign indicates a sign bit. weight word 2 47 2 46 ?2 40 2 39 ?2 32 2 31 ?2 25 2 24 2 23 ?2 16 2 15 ?2 12 ?2 8 2 7 ?2 0 transform parameters -47 46 ?40 39 ?32 31 ?25 24 23 ?16 7 0 internal source address generator -47 46 ?40 39 ?32 31 ?25 24 23 ?16 7 0 source address output sadr 23-0 -23 22 ?16 15 ?8 extended mode only tadr 11-0 11 ?4 3 ?0 kadr 7-0 fov = 0001 2 7 ?2 1 2 0 fov = 0002 ? 2 7 2 6 ?2 0 fov = 8000 2 7 ?2 1 2 0 utilization of the image boundary flags sv al and tv al as mentioned above, the TMC2302A provides two program- mable valid address, or boundary ?gs. the source valid ?g sv al is asserted when the current source image address output for that device's source image dimension is within the space de?ed by the con?uration parameters xmin and xmax, or ymin and ymax, or zmin and zmax, as appropriate. also, the target valid ?g tv al is available to indicate when the current target image address values fall within the space de?ed by the con?uration parameters umini, umaxi, vmini, vmaxi, and also wmini and wmaxi in three-dimensional systems. note that all of these parameters are each programmed into each individual TMC2302A. thus, the user could de?e two (or three) dif- ferent working spaces, one indicated by each ims device. figure 8 may help clarify the relationships among (x 0 , y 0 , z 0 ), (umin, vmin, wmin), and (umax, vmax, wmax), for the two-dimensional case. with positive ?st derivatives, (x 0 , y 0 ) and (umin, vmin) represent the upper left corners of the original image and the new destination ?ld, respectively. the lower right corner of the new trans- formed image is located at (umax, vmax); the location of the corresponding corner of the original image depends on the values of the derivatives. not to be confused with (x 0 , y 0 ), the points (xmin, ymin) and (xmax, ymax) de?e the ?sable?rectangular por- tion of the original image which is indicated by the valid address ?g sv al ; points (x, y) lying outside this region are ignored in most resampling and ?tering applications. speci?ally, the point (x 0 , y 0 ) is the location from which the TMC2302A system begins the image resampling sequence. every step beyond that point in the source image space is de?ed by the address generators implementing the image transformation polynomials. the valid source address ?g feature permits one to con- struct a mosaic of several abutting subimages in the (x, y) plane, without danger of edge effect interference between adjacent subimages. note in the ?ure that the upper right corner of the resampled source image lies outside the admis- sible region; in practice, the values fetched at these locations will not be included in the convolutional sums. one might, for instance, program these boundary values to alert the system that an edge is being approached and to modify the interpolation coef?ients appropriately, or simply to ignore pixel values outside the de?ed space. the tv al however is utilized somewhat differently. work- ing in unison with the target address working space de?ed by umin/umax, etc. the target address valid ?g could be programmed to delineate image areas other than the immedi- ate working space, and the ?g of each TMC2302A to indi- cate the unique regions anywhere within the target image. with this ?xibility, the user can generate windows, ?ic- ture-in-picture?composite multiple images, or simply switch to a background image or border color. to make tval func- tion properly, the used must set umin < umini < umaxi < umax; likewise for v and, if used, w.
TMC2302A product specification 22 preliminary information figure 8. pixel maps demonstrating source and destination image boundaries, violation flags, and image clipping (note shaded areas) x (xmin, ymin) (umin, vmin) (umin, vmin) (xmax, ymax) source image space target image space 65-2302-13 (umax, vmax) (umax, vmax) (x 0 , y 0 ) sval = 0 sval = 1 tval = 0 tval = 1 y u v real-time bilinear interpolation using the TMC2302A or tmc2301 image transformations and translations in bit mapped systems are done by taking an original (source) image, performing coordinate remapping and interpolation, then restoring the image into a new (destination) image space. the coordinates are remapped according to a transformation polynomial. the polynomial, evaluated at destination pixel addresses, maps the transformed pixel addresses (u, v) to pixel addresses in the original image addresses (u,v) to pixel addresses in the original image (x, y), i.e., (x, y) is a polynomial function of (u, v). notes: 1. coordinate transformation: each pixel in (u, v) space is mapped to a location in (x,y) space. 2. interpolation: unless the pixel in (u, v) space coincides with one in (x, y) space, its amplitude must be estimated as a weighted average of those of the surrounding pixels in (x, y) space. if the interpolation is done serially, throughput suffers in proportion to the size of the interpolation kernel. however, the interpolation can also be performed in parallel to preserve throughput, as discussed here. 65-2302-14 (x0,y0) new pixel (u,v) (umin,vmin) v u (umax,vmax) (umin,vmax) note 1 note 2 (0,0) y x original (source) image new (target) image inter- polator
product specification TMC2302A 23 preliminary information the TMC2302A image manipulation sequencer the TMC2302A is a controller/address generator, around which an image ?tering and resampling system can be built. under limited supervision from an external controller, the TMC2302A will generate the sequence of memory read and write addresses to transform, resample, and/or ?ter an image. in all cases, it fetches data from one image buffer, governs its convolution with a user-speci?d kernel of coef?ients, and directs the results to another image memory space. with 24-bit source address buses the device can operate from a source frame size of, for example, 64k x 64k pixels with spatial resolution of 1/256th pixel. a simpli?d block diagram of the TMC2302A is shown in figure 9. although the 24 source addresses bits of each TMC2302A can be designed arbitrarily with the source image address bus, assume for the current discussion that bits sadr (19:8) will correspond to the source image address and that sadr (7:4) therefore denote subpixel post- poning to 1/16 pixel resolution. the basic 2-d system, shown in figure 10, consists of data source and destination memories, coef?ient lookup table, multplier-accumulator, TMC2302A parameters to de?e the transform and starts the operation. it may also control the loading of the source image into ram and provide the screen refresh, if needed. figure 9. TMC2302A block diagram 65-2302-15 asynchronous host interface idat 15-0 iadr 6-0 ics iwr control parameter registers control noop synchronous host interface init clk sync target address generator source address generator source memory interface convolutional control target memory interface sync flags oes sadr 23-0 sval oek acc twr kadr 7-0 oet tval tadr 11-0 end done walk counter
TMC2302A product specification 24 preliminary information figure 10. basic 2-d image transformation systems 65-2302-16 2302a row (x) coeff. buffer ram 1024 x 8 2302a column (y) clock 12 data control tadr 11-0 address 12 source address 24 source image buffer ram 8 data in 8 here 4 x 4k words image size one set per color component (not recommended for composite video) one set per color component 8 one set per color component 8 data out 24 12 sadr 19-8 tadr 11-0 sadr 7-4 kadr 1-0 clk x,y,p x 8 x 8 mac d out 8 y destination image buffer ram destination address address 6 4 sadr 19-8 a a inexact transformations in many cases, evaluation of the transformation polynomial results in a non-integer result (non-integer address in the x, y image space). in such cases, the mapping from original image to transformed image will be inexact. when this occurs, the user has the option of accepting the pixel ?ear- est?to the address generated, or performing interpolation, a weighted average of nearby pixel values. using the pixel nearest the address generated is the fastest method since one transformed pixel can be generated on every cycle. the resulting image will include jagged biasing artifacts, however. performing several transformations on the same image will further degrade the resulting image. one cycle bilinear interpolation a better image can be obtained by ?ding the four pixels nearest the address generated and performing a weighted averaging to determine the new pixel value. this is known as bilinear interpolation. the TMC2302A eases the control logic required for such a function by performing a ?alk? around the four closest pixels in the source image space. essentially, the TMC2302A generates the addresses of the four walk cycles, and the current source pixel is multiplied by a weighting factor and accumulated by the external multi- plier accumulator. at the end of the walk, the accumulated result from the four nearest pixels is written into the destina- tion image ram and the TMC2302A proceeds to the next group. the obvious disadvantage to using bilinear interpola- tion is that one new destination pixel is generated only on every fourth cycle, reducing the output bandwidth by a factor of four. one method of ?eal-time?bilinear interpolation consists of using four memories, each containing the entire source image. the storage arrangement of the pixels within each bank is staggered so that a single address fed to the memories will result in the access of the proper four pixel group. the TMC2302A is programmed to generate the nearest neighbor address and the four nearest pixels are accessed simultaneously and input to the four independent multipliers of a tmc2246 quad multiplier chip. the four pixels are mul- tiplied by their associated weighting factors and added to determine the destination pixel sum. the major drawback of this method is the prohibitive cost for additional memory required to store four copies of the entire source image. for large images, the memory cost and additional board space makes this method unattractive.
product specification TMC2302A 25 preliminary information a more ef?ient method is to divide the original source image into a ?our-color checker board?and to store it into four separate pixel memory banks, each containing 14th of the source image. since the image is separated into four memories rather than duplicated, no additional image memory is required. the goal is to separate the image so that any square of four adjacent pixel locations can be accesssed simultaneously. thus, the user must organize the memory such that the four pixels of any cluster will reside in separate memory banks. with this method, only one set of address generators (TMC2302As) is necessary, and only a slight address modi?ation is necessary to guarantee that the correct group of pixels is accessed and output to the multipli- ers. since all pixels are accessed simultaneously, no ?alk? is performed, and the TMC2302A system is able to generate one destination pixel on each clock cycle. for example, a 1024 x 768 image can be generated every 20ms for a frame refresh rate of 50hz. this method which will be described below. using banded pixel memory the TMC2302A should be programmed to do ?earest- neighbor?transformations (kernel, k = 0 and the x 0 and y 0 start boundaries programmed without 1/2-lsb truncation debiasing to force address truncation when evaluating the transformation polynomial for the nearest-pixel address). the biased x 0 and y 0 guarantee that when the exact pixel address falls within the region of four pixels, the upper left- most pixel will always be selected as ?earest-neighbor. the key to performing real-time bilinear interpolation is to arrange the pixels in memory so that the four pixels of every grouping will be stored in separate memories. the four near- est pixels will form a square. figure 11 shows a sample 512 x 512 pixel image and the arrangement into four sepa- rate memory banks designated a, b, c, and d. it can be seen from the ?ure that any (square) grouping of four pixels will have one pixel located in each bank. thus, one memory sector will hold even row-even column pixels, another, even-row-add column pixels, etc. figure 11. source image pixel arrangement a 0,0 (0,0) b 0,0 (1,0) a 1,0 (2,0) b 1,0 (3,0) a 2,0 (4,0) b 2,0 (5,0) a 3,0 ? 255,0 (6,0)?510, 0) b 255.0 (511, 0) c 0,0 (0,1) d 0,0 (1,1) c 1,0 (2,1) d 1,0 (3,1) c 2,0 (4,1) d 2,0 (5,1) c 3,0 ? 255,0 (6,1)?510,1) d 255,0 (511,1) a 0,1 (0,2) b 0,1 (1,1) a 1,1 (2,1) b 1,1 (3,2) a 2,1 (4,2) b 2,1 (5,2) a 3,1 ? 255,1 (6,2)?510,2) b 255,1 (511,2) c 0,1 (0,3) d 0,1 (1,3) c 1,1 (2,3) d 1,1 (3,3) c 2,1 (4,3) d 2,1 (5,3) c 3,1 ? 255,1 (6,3)?510,3) d 255,1 (511,3) a 0,2 (0,4) b 0,2 (1,4) a 1,2 (2,4) b l,2 (3,4) a 2,2 (4,4) b 2,2 (5,4) a 3,2 ? 255,2 (6,4)?510,4) b 255,2 (511,4) c 0,2 (0,5) d 0,2 (1,5) c 1,2 (2,5) d 1,2 (3,5) c 2,2 (4,5) d 2,2 (5,5) c 3,2 ? 255,2 (6,5)?510,5) d 255,2 (511,5) a 0,255 (0,510) b 0,255 (1,510) a 1,255 (2,510) b 1,255 (3,510) a 2,255 (4,510) b 2,255 (5,510) a 3,255 ? 255,255 (6,510)?510,510) b 255,255 (511,510) c 0,255 (0,511) d 0,255 (1,511) c 1,255 (2,511) d 1,255 (3,511) c 2,255 (4,511) d 2,255 (5,511) c 3,255 ? 255,255 (6,511)?510,511) d 255,255 (511,511) subscripts i, j for a, b, c, and d denote relative addresses in memory respectively. the ordered pairs (a, b) denote the physical (x,y) pixel locations and the TMC2302A sapr(x) and sadr(y) address outputs. the pixels of the original image should be stored in the source ram banks as shown in figure 12. the original source image can be loaded by decoding the TMC2302A least signi?ant address bits (sadr x (8). sadr y (8) to determine the memory bank for the pixel while the most-signi?ant address bits (sadr x (19:9), sadr y (19:9)) are used as common address lines to all four memory banks.
TMC2302A product specification 26 preliminary information in the following discussion, the TMC2302A address outputs sadr x and sadr y will be designated as: interpolation kernel figure 13. TMC2302A serial walk sequence in real time bilinear resampling, this is executed in parallel when the transformation polynomial is evaluated and the resulting pixel address falls within a group of four nearby pixels (non-integer result), the TMC2302A will always choose the upper leftmost pixel (p ij ) as the nearest neighbor (due to the fractional address truncation in the x and y direc- tions). since the four pixels will reside in independent banks, the upper leftmost pixel might be located in any of the four memory banks (a,b,c, or d). the bank which contains the nearest neighbor must be known, since in each case, different memory address modi?ation is required to select the correct pixel from each bank. horizontal source xa 0 least-signi?ant horizontal source x-address bit sadr x (8) xa m upper horizontal source address bits sadr x (19:9) ya 0 least-signi?ant vertical source y-address bit sadr x (8) ya m upper vertical-source address bits sadr y (19:9) figure 14. possible selections for nearest neighbor memory address modi?ation using the address lsbs (xa 0 , ya 0 ) from each TMC2302A external logic can determine which bank contains the nearest neighbor. (this same decoding is used when loading the original image into the source image rams.) case* xa 0 ya 0 nearest neighbor (upper leftmost) pixel 1 0 0 a memory bank contains nearest neighbor 2 1 0 b memory bank contains nearest neighbor 3 0 1 c memory bank contains nearest neighbor 4 1 1 d memory bank contains nearest neighbor *from figure 14 above 65-2302-17 *-1 *-2 *-3 *-4 b a b a b a b c d c d c d d b a b a b a b d c d c d c d TMC2302A ad- dress bank a bank b bank c bank d xa m , ya m xa 0 ya 0 = 00 xa 0 ya 0 = 10 xa 0 ya 0 = 01 xa 0 ya 0 = 11 00 a 0,0 b 0,0 c 0,0 d 0,0 01 a 0,1 b 0,1 c 0,1 d 0,1 02 a 0,2 b 0,2 c 0,2 d 0,2 0 255 a 0,255 b 0,255 c 0,255 d 0,255 10 a 1,0 b 1,0 c 1,0 d l,0 11 a 1,1 b 1,1 c 1,1 d 1,1 12 a 1,2 b 1,2 c 1,2 d 1,2 255 254 a 255,254 b 255,254 c 255,254 d 255,254 255 255 a 255,254 b 255,254 c 255,254 d 255,254 p i, j p i, j+1 * - actual pixel p i+1, j p i+1, j+1
product specification TMC2302A 27 preliminary information addressing for each memory bank (a, b, c, d) is done using the uppermost address bits (xa m ) of the TMC2302As. the lsb of each TMC2302A is used to determine both the upper leftmost pixel and the address modi?ation required. in the following paragraphs, the lower case subscripts (i,j) denote the address of a pixel within a given memory bank (a, b, c, or d), and xa, ya are used to denote physical address outputs of the TMC2302A pairs. pixel address modi?ation use to access the correct four pixel group is determined as follows: case a: a i,j is nearest upperleft neighbor, (no address modi?ations) (xa 0 = ya 0 = 0) a i,j b i,j * c i,j d i,j figure 15. pixel memory mapping for a = upper leftmost memory addressing becomes: a address = xa m , ya m b address = xa m , ya m c address = xa m , ya m d address = xa m , ya m i.e., no modi?ation is required. case b: b i,j is upperleft neighbor, (modify x component of a & c memory addresses) (xa 0 = 1, ya 0 = 0) b i,j a i + 1,j * d i,j c i + 1,j figure 16. pixel memory pattern for b = upper leftmost memory addressing becomes: a address = (xa m + 1, ya m ) b address = (xa m , ya m ) c address = (xa m + 1, ya m ) d address = (xa m ya m ) case c: ci,j is upperleft neighbor, (modify y component of a & b memory addresses) (xa 0 = 0, ya 0 = 1) c i,j d i,j * a i,j + 1 b i, j + 1 figure 17. pixel pattern for c = upper leftmost memory addressing becomes: a address = xa m ya m + 1 b address = xa m , ya m + 1 c address = xa m , ya m d address = xa m , ya m case d: di,j is the nearest neighbor (modify a, b & c addresses, x and y components) (xa 0 = 1, ya 0 = 1) d i,j c i + 1,j * b i, j + 1 a i +1,j +1 figure 18. pixel pattern for d = upper leftmost memory addressing becomes: a address = xa m + 1, ya m + 1 b address = xa m , ya m + 1 c address = xa m + 1, ya m d address = xa m , ya m taking a close look at the address modi?ations required for each case above, a simple pattern can be seen. this pattern leads to a set of address modi?ation ?ules?based on the values of the least-sign?ant address bits from the tmc2301s (xa 0 and ya 0 ). these rules are: when ya 0 = 0. (case a & b) no modi?aton to the y address component (ya m ) is necessary. when ya 0 = 1, (case c & d) the y component (ya m ) of addresses to the a & b memory banks must be incremented by 1. when xa 0 = 0. (case a & c) no modi?ation to the x address component (xa m ) is necessary. when xa 0 = 1, (case b & d) the x component (xa m ,) of addresses to the a & c memory banks must be incremented by 1. a system can easily be designed to modify the pixel memory addresses according to the above criteria, to select the correct four pixels to be interpolated. rather than actually perform- ing a ?onditional?address increment as discussed above. it requires less logic simply to add the lsb address bit to the memory bank addresses (xa m , ya m ). figure 12 shows the logic to perform the required address modi?ations. the addition (xa m , + xa 0 , ya m , +ya 0 ) can be done using half-adders with the xa 0 (ya 0 ) address output of the TMC2302A connected to the carry-in of each adder. it can also be done using high-speed programmable logic.
TMC2302A product specification 28 preliminary information note: only modi?ations to the source image memory are necessary. the destination image memory may be arranged in a linear or other type array as required by the refresh circuitry. coef?ient memory typically, the 4 highest fractional source address bits from each TMC2302A (sadr (7:4) in the example) are used to re?ct the offset from the nearest xa (ya) pixel location. with spatial resolution of 4 bits in both the x and y direc- tions, there can be as many as 256 unique coef?ient values. this requires a coef?ient memory of at least 256 bytes. however, as shown below, each of the four different cases requires its own set of 256 coef?ients. one-cycle bilinear interpolation requires four independent coeff?ient memories, so that a parallel multiplication can be performed with the four pixel values. figure 19. memory address modification 65-2302-18 TMC2302A (row) sadr (19:9) sadr (8) tadr (11:0) TMC2302A (column) ya ya o v bank a x 11-1 y 11-1 11 11 out 8* to mpy a bank c x 11-1 y 11-1 out 8 to mpy c bank b x 11-1 y 11-1 out 8 to mpy b bank d x 11-1 y 11-1 out 8 to mpy d to dest. memory 11 11 12 12 u xa xa 0 address in tadr (11:0) sadr (19:9) sadr (8) u *number of bits of intensity per pixel, per column component, typically 8 to 12.
product specification TMC2302A 29 preliminary information figure 20. intrapixel resolution 16 steps/pixel 65-2302-17 16 steps p i, j+1 p i, j p i +1, j p i +1, j+1 256 discrete coefficient values similar to determining the correct four pixel group, the coef- ?ients must take into account the memory bank (a, b, c, or d) that contains the upper leftmost pixel, and adjust the coef- ?ients accordingly. these adjustments are necessary since the fractional address outputs (sadr x 7:4), sadr y (7,4) from the TMC2302As re?ct the spatial distance only from the upper leftmost pixel within the pixel group. assuming that the fractional addresses sadr x (7:4) and sadr y (7:4) plus the integer lsbs sadr x (8) and sadr y (8) are to be used directly to address the 1024-byte coef?ient memory, the loading of the coef?ients is shown below with f x = sadr x (7:4) and f y = sadr y (7:4) case a through d are the same as discussed previously for the pixel address modi- ?ations. case a: a is nearest neighbor (xa 0 = 0, ya 0 = 0) coeff a = (1 - f x ) * (1 - f y ) coeff b = (f x ) *(1 - f y ) coeff c = (1 - f x ) * (f y ) coeff d = f x * f y case b: b is nearest neighbor (xa 0 = 1, ya 0 = 0) coeff a = f x * (1-f y ) coeff b =(1-f x ) * (1-f y ) coeff c = f x * f y coeff d = (l-f x )f y case c: c is nearest neighbor (xa 0 = 0, ya 0 = 1) coeff a = (1- f x ) f y coeff b = f x f y coeff c = (1 - f x ) (1 - f y )coeff d = f x * (1 - f y ) case d: d is nearest neighbor (xa 0 = 1, ya 0 = 1) coeff a = f x f y coeff b = (1 - f x )f y coeff c = f x * (1 - f y ) coeff d = (1 - f x ) (1 - f y ) incorporating the concepts outlined in this discussion, the ?al system for one-cycle blinear interpolation is shown in figure 21. this ?ure shows a small increase in logic over the basic 2-d system shown in figure 10. the additional logic required includes: tmc2246 (rather than a single mul- tiply/accumulate), and three additional coef?ient memories. some additional decoding logic is required to load the four pixel memory banks as well as some data and address pipe- lining (registering) to meet timing requirements. the solu- tion, however, provides an increased pixel bandwidth, by a factor of four, and only a small increase in part count.
TMC2302A product specification 30 preliminary information figure 14. one-cycle bilinear interpolation system related products tmc2301 image resampling sequencer tmc2246a image filter tmc2249a digital mixer tmc2242b half-band filter 65-2302-20 TMC2302A (row) sadr (8:4) 5 TMC2302A (column) +1 +1 d c b a coeff. ram 1k x 8 5 tdar d c b a source image ram 10 10 10 10 8 8 8 8 tmc2246a dest. image ram sadr (19:9) sadr (8) tadr sadr (8:4) sadr (19:9) sadr (8)
product specification TMC2302A 31 preliminary information notes:
TMC2302A product specification 32 preliminary information notes:
product specification TMC2302A 33 preliminary information notes:
TMC2302A product specification 34 preliminary information mechanical dimensions 121-lead ppga package d pin 1 identifier top view cavity up d1 p l a2 a ? e ?2 a1 a .080 .160 2.03 4.06 symbol inches min. max. min. max. millimeters notes a1 .040 .060 1.01 1.53 .215 5.46 a2 .125 3.17 ? .016 .020 0.40 0.51 d 1.340 1.380 33.27 35.05 2 2 sq d1 .110 .145 2.79 3.68 e .050 nom. 1.27 nom. 1.200 bsc 30.48 bsc .100 bsc 2.54 bsc l l1 .170 .190 4.31 4.83 .003 .076 m13 13 120 120 3 4 n p ?2 notes: 1. 2. 3. 4. 5. 6. pin #1 identifier shall be within shaded area shown. pin diameter excludes solder dip finish. dimension "m" defines matrix size. dimension "n" defines the maximum possible number of pins. orientation pin is at supplier's option. controlling dimension: inch.
product specification TMC2302A 35 preliminary information mechanical dimensions (continued) 120-lead mqfp package a d d1 e1 e e pin 1 identifier a2 a1 a b base plane seating plane see lead detail c 0 ? min. r 0.063" ref (1.60mm) lead detail l .20 (.008) min. .13 (.005) r min. -c- ccc c lead coplanarity notes: 1. 2. 3. 4. 5. all dimensions and tolerances conform to ansi y14.5m-1982. controlling dimension is millimeters. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "b" dimension. dambar cannot be located on the lower radius or the foot. "l" is the length of terminal for soldering to a substrate. "b" & "c" includes lead finish thickness. a .154 3.92 symbol inches min. max. min. max. millimeters notes a1 .010 .25 .018 .45 a2 .125 .144 3.17 3.67 b .012 3, 5 .30 .009 .23 c .005 .13 d1/e1 1.098 1.106 27.90 28.10 .0315 bsc .80 bsc e l .026 .037 .65 .95 120 120 30 30 4 5 n nd a 0 ? 7 ? 0 ? 7 ? .004 .10 ccc d/e 1.219 1.238 30.95 31.45 .13/.30 .005/.012
TMC2302A product specification pr eliminar y infor mation 5/20/98 0.0m 001 stock#ds70002302a 1998 fairchild semiconductor corporation life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1 . life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2 . a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com o r dering in f ormation p r oduct number t emperature range speed grade screening p a c k age p a c kage marking TMC2302Ah5c 0 c to 70 c 30 mh z commercial 120 pin plastic pin grid array 2302ah5c TMC2302Ah5c 1 0 c to 70 c 40 mh z commercial 120 pin plastic pin grid array 2302ah5c1 TMC2302Akec 0 c to 70 c 30 mh z commercial 120 lead metric quad flatpack 2302akec TMC2302Akec 1 0 c to 70 c 40 mh z commercial 120 lead metric quad flatpack 2302akec1

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